Integrated circuit designs, such as those for modern system-on-a-chip (“SOC”) devices, continue to grow is size and complexity. Shrinking transistor sizes mean that more and more transistors can be included in a circuit design once fabricated as an integrated circuit chip (“chip”), while a greater number of features or components can be packed on the chip. The chip may be any type of integrated circuit fabricated, whether on a single substrate or multiple interconnected substrates. Functional verification of such devices is usually included as part of the circuit design flow to help ensure that the fabricated device functions as intended.
The increasing size and complexity of the circuit designs to be verified (devices under test, “DUT,” also known as designs under verification, “DUV”) mean that the functional verification portion of the design cycle is increasing in length. The verification stage may in some case be the longest stage of the design cycle. For example, running a simulation on a host computer to verify a SOC, or even a sub-portion of the SOC, written in the register transfer language (“RTL”) design abstraction may take anywhere from hours to days. Certain hardware functional verification systems may leverage high-performance hardware to increase the speed of the verification stage, including a plurality of interconnected processor chips. Such systems are also referred to as “emulators” herein.
FIG. 2 illustrates a generic D flip-flop 200, having a data input port D, an enable port E, a clock port, and a Q output port. The D flip-flop 200 tracks the D input, capturing the D input on a clock edge of the clock, which may be a rising edge, a falling edge, or another trigger. Output Q then outputs the stored D input after the clock edge. In other words the state of output Q tracks the state of data input D, but delayed by a clock cycle. Enable F enables, or not, the D flip flop. Such flip flops may also allow for the capability (not illustrated) to force the flip flop into a set or reset state, where the data D input and clock are ignored.
The circuit designs of a user's DUT to be mapped to the emulator frequently contain flip-flops (“user flops”) that need to be implemented in an emulator during functional verification. Prior art processor-based emulators modeled user flops inefficiently. For example, the user flop models would need multiple memory locations to store the state of the user flop, and thus multiple instructions for the multiple memory locations. In addition, the models did not always allow for the modeling of the full functionality of a general purpose flip-flop, such as resets and global enables. Thus, a more efficient mechanism to model user flops in a processor-based emulator is desirable to increase emulation capacity and efficiency in such emulators.